Communications over digital lines and other media often use communication protocols that require synchronized data transmission. However, even synchronously transmitted digital data over lines experience timing shifts or phase changes during the transmission. Such timing shifts, known as jitter, can result in data lags which in length, can be anywhere from a fraction of a pulse to several pulse periods. Because of these delays, any attempt to read data at the expected or "synchronized" arrival time may result in errors. Accordingly, different approaches have been followed to determine the arrival of a block of data.
One approach has been to utilize digital phase lock loop methods to synchronize the data sampling or reading with the data arrival. However, one drawback of utilizing phase lock loop (PLL) methods is that the PLL circuits are complex and, in an integrated circuit, can consume an undesirable amount of power and circuit space. PLL circuits are generally constructed with feedback loops which can become unstable. PLL systems also increase the device cost. Accordingly, a simpler system which costs less and utilizes less power and circuitry is desirable.
Another approach has been to utilize traditional L.C. tanks. However, LC tanks are known to introduce jitter and exhibit poor stability over temperature and time.
The T1 transmission standard uses an "alternate-mark-inversion" (AMI) format. The AMI format consists of "0" bits being represented by the absence of a pulse while "1" bits are represented by pulses of alternating polarity. The time average signal voltage of T1 data transmissions, therefore, is zero volts. Additionally, the T1 standard frequency for data transmission is 1.544 Megabits per second. Because a T1 line carries twenty four channels plus one framing bit, each channel transmits at a rate of 64 kilobits per second. Additionally, T1 transmission is based on twisted pair wiring, with separate pairs being used for the transmit and receive sides of the T1 line. T1 lines also require a repeater circuit at least every 6,000 feet to regenerate the signals which are attenuated and phase distorted.
One known problem of digital transmissions at such frequencies is that line inductance and line capacitance cause significant pulse distortion and attenuation. Because a pulse is essentially a signal having a large multitude of varying frequency components, the line inductance and capacitance distort the component signals by phase shifting and attenuating the frequency components in differing amounts. The overall result is to "smear" the original pulse received at the input end of the cable to produce an attenuated signal having ripple waves superimposed thereon. Accordingly, the phases of these signals must be realigned and the attenuation must be compensated to approximately reconstruct the initial pulse.
After a pulse is reconstructed, another problem is to determine that a pulse has arrived so that the optimal sample point of the pulses of a digital stream may be determined. In a PLL system, the timing of the pulses are known because of the synchronized characteristics of phase lock loop. However, as discussed before, it would be advantageous to utilize a circuit simpler than a PLL. Accordingly, a line may be periodically sampled to determine the presence of the first pulse of a data stream. If pulses were received in an ideal shape without jitter, then the sample rate could be no faster than the actual pulse rate. However, because of pulse distortion and jitter, it is desirable to sample a digital stream for data reading purposes at or near the middle of the pulse. However, to sample in the middle of a pulse, the presence of a pulse must be detected immediately after arrival of the leading edge of the pulse. Thus, if the timing of a pulse is not known exactly, the amount of time after arrival of a leading edge should be minimized by increasing the sample rate of a transmission line.
The sample rate of the oscillator must be several times faster than the signal it is tracking to properly track the instantaneous jitter of the desired signal. For example, the T1 specification requires that 0.4 unit intervals (UI) of jitter modulating at 100 KHz be tolerated while properly determining if a 1 or a 0 has been received. At the T1 rate of 1.544 megabits/sec., a 32x oversampling clock will sufficiently track the required jitter to meet the specification. Thus, what is needed is a stable system which increases the sample rate to satisfy the T1 standard.